We offer a position as an

Early Stage Researcher (M/F/D)

in the Marie Skłodowska-Curie Innovative Training Network Project MENELAOS^NT in the field

Design of an AIC CMOS vision system for spatio-temporal event detection (ESR2)

Machine learning and, in particular deep learning techniques constitute a unique framework for analog to information (AIC) compression. Nevertheless, the feasibility of a hardware implementation of such power and memory-hungry algorithms calls for new strategies that benefit from the low power features of analog and mixed-signal design techniques. The final goal of this work will be the design of a low Size, Weight and Power (SWaP) AIC CMOS vision system for spatio-temporal event detection through deep learning tracking techniques. The system will comprise a CMOS vision chip with focal-plane processing and a general-purpose embedded hardware such as an FPGA. The CMOS vision chip will acquire the video and provide the detections that trigger the tracking. The baseline of our tracking approach will be state-of-the-art neural networks that learn similarity functions. Compressive deep learning techniques like binary weighting, weight sharing and pruning will be required to fit such networks on the FPGA.

The successful candidate will be employed for a maximum period of three years full-time equivalent and receives a generous financial package plus an additional mobility and family allowance according to the rules for Early Stage Researchers (ESRs) in an EU Marie Sklodowska-Curie Actions Innovative Training Networks (ITN). A career development plan will be prepared for each fellow in accordance with his/her supervisor and will include training, planned secondments and outreach activities in partner institutions of the network. The ESR fellows are supposed to complete their PhD thesis by the end of the 3rd year of their employment. For more information please visit the Marie Sklodowska-Curie Actions Innovative Training Networks website.

YOUR TASKS

• Definition of tasks of interest for ex- and in-situ explorations by the consortium.
• Evaluation of different algorithms for spatial localization of foreground events by the CMOS vision sensor chip through different software frameworks like OpenCV or Caffe.
• Design of the CMOS vision sensor chip.
• Hardware-oriented state-of-the-art siamese neural network for tracking through deep learning compression techniques like binary weighting, pruning, etc.
• FPGA implementation of a hardware-oriented siamese neural network.
• On-board evaluation of the final AIC CMOS vision system for spatio-temporal event detection.

PROFILE

• Master of Science in Electrical Engineering, Electronics Technology, Electrical Engineering Technology, Electrical and Computer Engineering, Physics, Industrial Engineering, Information Technologies or related fields
• ESRs must demonstrate that their ability to understand and express themselves in both written and spoken English is sufficiently high for them to derive the full benefit from the network training. Non-native English speakers are required to provide evidence of English language competency. (TOEFL … )
• enthusiasm, creativity, team-work capacity, hard-working capability, resilience

Planned Secondments

• INSITU, Vigo, Spain, Prof. Dr. P. Arias Sánchez, 6 months, testing of the fabricated devices on mobile platforms.

Additional Information

It is desirable for the applicants to have some basic knowledge on:

• Analog and digital CMOS circuit design with modern CAD tools like Cadence or similar frameworks
• Solid-state semiconductor devices and simulation frameworks (ATLAS, Sentaurus,…)
• Programming languages; C, C++, Python and Matlab

The following scientific publications by members of the USC team provide a more clear insight on the topic of this PhD:

1. B. Blanco-Filgueira et al., “Deep Learning-Based Multiple Object Visual Tracking on Embedded System for IoT and Mobile Edge Computing Applications”, IEEE Internet of Things Journal, vol. 6, no. 3, pp. 5423-5431, 2019
2. D. Gacía-Lesta et al., “In-pixel Analog Memories for a Pixel-Based Background Subtraction Algorithm on CMOS Vision Sensors”, International Journal of Circuit Theory and Applications, vol. 46, no. 9, pp. 1631-1647, Sept. 2018
3. M. Suárez et al., “Low-Power CMOS Vision Sensor for Gaussian Pyramid Extraction”, IEEE International Journal of Solid-State Circuit, vol. 52, no. 2, pp. 483-495, 2017

For further information, please visit: https://citius.usc.es/equipo/persoal-adscrito/paula-lopez-martinez